CSP  COS


Product Overview
 
A special designed structure for DRAM devices. Ball grid array substrate is used instead of conventional lead frame to reduce package weight and size. A slot at the center of substrate is formed to accommodate the interconnection between center bonding pads of chip and solder balls. Better electrical performance under high frequency can be achieved due to signal transmission path reduction.



Application
 
  • Personal computers or notebooks
    -- DRAM module
  • Telecommunication products
    -- Cellular phone
  • Consumer products
    -- Camcorder
    -- Personal digital assistant
    -- Digital camera
    -- Memory card



Features
 
Laminate substrate with ball grid array outline
Small footprint
Low profile (max. thickness 1.0mm)
Light weight
Better electrical performance under high frequency conditions
Double density and stacked structure is possible
 



Performance
 
Electrical
 
  mm R (mohm) CL (pF) Cm (pF) Ls (nH) Lm (nH) GND (nH) Pwr (nH)
Min 4.7 50 0.52 0.14 3.44 0.75 2.55 2.63
Max 9.6 105 1.23 0.35 7.4 2.1 6.87 6.85
 
Thermal
 
COS 54L
Thermal Path Ratio
Die 49.6%
PCB(BT,4L) 14.4%
Substrate& Compound 29.8%
Ball 6.2%



Standard Process/Materials
 
Wafer Mount  
Wafer Saw/ Clean  
2nd Optical (Gate)  
Die Attach  
Die Attach Cure  
Wire Bond Gold Wire: 99.99% Au
3rd Optical (Gate)  
Liquid Encapsulation  
Post Mold Cure  
Top Side Laser Marking  
Ball Mount  
Singulation  
Final Visual Inspection (Gate)  
Packing  
 
Optional process: wafer back grinding/die coating



Packing & Shipping
 
Packaging tray
 
Body Size Lead count Vendor
12.45x23.00 416 HWA SHU



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