ASE Kaohsiung TOP > Products > CSP > Leadless > LGA

CSP  Leadless  LGA Product Overview   Land grid array (LGA) uses laminate substrate to form the landing pad and the exposed pad for performance enhancement. It is essentially a BGA minus the solder balls. LGA's advant-age over other leadless packages is its flexible routing and multi-chip module capability LGA is also a thinner (down to 0.66 mm) and lighter CSP. LGA technology has been developed for lead free solution and space reduction on mother boards. This type of package has chip size solution based on mature laminated substrate technology and material. Application   LGA is suitable for high performance ICs like Single Chip, CPU, Logic and Memory. Common applications for this type of package includes:   Telecommunication products   Cellular phone-RF Devices Wireless LAN Portable products   Personal digital assistants   Digital cameras MP3 players   Memory card   SD cards MS cards PCMCIA Features   Thinner, lighter and smaller Chip-Scale Package Mature standard matrix BGA assembly process Higher yield/quality Higher through put Lower cost Space reduction at system level Pb free solution Excellent electrical and thermal performance Reliability   Package Level MSL JEDEC level 2 85°C,/60% RH 168 hours PCT 121°C/100% RH/2 atm 168 hours TCT -65°C~150°C 1000 cycles HTST 150°C 1000 hours HAST 130°C/85% 100 hours   Board Level Temp -40°C~125°C 2500 cycles no failed Bending 1mm deflection/2Hz No available Drop 1m height No failed Design Rule     Item Description Criteria (um) G-A Exposed bond finger metal (Double bond) 406 min. G-B Exposed bond finger metal (Single bond) 280 min. G-C Max. bond wire length 3556 um (140 mils) Max. G-D Bond wire center to adjacent bond pad center 50 min. G-E Die bond pad pitch 50 min. G-F Bond wire span over bond finger before target point 90 min. G-G Lead length in line with bond wire beyond target point 45 min. G-H Bond wire center to adjacent bond finger (Bottom die only) 63.5 min. G-I Bond finger width 95 min. G-K Wire center to wire center distance 45 min. G-L Wire bond pad size 45 min. G-M Bonding pad to package edge 1000 min. Performance   Electrical Characterization   Unlike BCC and MCC, some LGA packages have signal traces to connect the peripheral I/O pads on chip with array landing pads in the substrate. Thus the electrical data is not attributed to the gold wire only. Almost all the LGA substrates are customized. The RLC data is therefore variable. (Contact ASE R&D for electrical data.)   Electrical Capacitance 0.20 pF Inductance 0.20 nH Resistance@100 MHz 4.64 mohm   Ground Path Capacitance 2.37 pF Inductance 0.27 nH Resistance@100 MHz 4.72   Thermal Characterization     (1mm=39.37mil; 1mil=25.4um) Standard Process/Materials   Wafer Backgrinding Wafer mount) Wafer saw/clean 2nd optical (Gate)   Die attach Epoxy cure Plasma clean   Wire bond Gold wire: 99.99% Au 3rd optical (Gate) Plasma clean Mold Post mold cure Top side laser marking   Singulation Final visual inspection (Gate)     Packing       Optional process: Wafer back grinding     Package Offering     2008 ASE Kaohsiung, All rights reserved. Terms of Use