ASE Kaohsiung

CSP Leadless

QFN
BCC/BCC+/BCC++
LGA

Product Overview

Leadless packages have minimum interconnects by saving the leads and making the connection from bonding wire to the PCB through tiny terminals or fingers. In this manner, leadless packages exhibit smaller dimensions than common leaded packages (e.g. TSSOP), and demonstrate the capability of CSP. Leadless packages only suffer the effect from bonding wire; therefore, the electrical parasitic can be under control. To conduct the heat effectively, some leadless packages expose the die pad to the ambience. This pad can be soldered to PCB to provide direct heat conduction and electrical grounding.

Leadless package is very suitable for low pin count, and high frequency ICs (RFICs, analog ICs). ASE offers from 8 to less than 100 I/O leadless packages as of now.

Features

PKG type	Lead count available	Body width (mm)	Overall thickness (mm)	Lead pitch (mm)
BCC/ BCC+/ BCC++	8~ 64	2.8X3.8~ 9X9	0.75	0.5/0.65
MCC (QFN)	4~ 84	3X3~ 10X10	0.9	0.4/0.5*/0.65/0.8
LGA	32~52	5X5~ 12X12	0.8~ 0.9	0.5/0.65

* 0.5 mm pitch is ASE standard

Reliability Test Plan

All the leadless packages selected for temperature/humidity test and temperature cycles are subject to precondition process per JEDEC moisture Level 3 (Level 1 for BCC, and Level 2 for BCC++) prior to environmental stress. Test criterion is zero defect out of 45 sampling units.

Temp/Humidity Test	85°C/ 85% RH, 1000 hr.(JEDEC 22- A101)
Pressure Cooker Test	121°C/ 100% RH/ 15 PSIG, 300 hr/ 168 hr (for LGA)(JEDEC 22- A102)
Temp Cyclic Test	-65°C~150°C, 1000 cycles(MIL-STD-883-1010.7)
High Temp Storage Test	150°C, 1000 hr.(JEDEC 22- A103)
High Accelerated Stress Test	130°C/ 85% RH/ 33.5 PSIA, 100 hr. (JEDEC 22- A110)