| Product Overview |
| |
| CSP (chip scale package or chip size package) is a package that has an area of not more than 120% of the die. It is suitable for compact 2nd-level packaging efficiency. With better protection by ruggedized encapsulation and better 2nd-level reliability (or board level reli-ability), CSP prevails over the direct chip attach (DCA) and chip on board (COB) technology. This package makes the IC sturdy enough for easier handling, and testability. Providing lowcost test and burn-in, CSP is a substitute for known good die with comparable electrical performance. In addition to required signal and power transmission contacts, some CSPs provide a direct thermal path for heat removal from the chip. The applications of CSP include memory ICs, RFICs, and communication ICs. |
|
| CSP Offerimgs |
| |
| BCC/BCC+/BCC++ |
| BCC is a leadless package suitable for low pin count (<100) and high frequency ICs (up to 12GHz and above). With a direct heat path through exposed die pad to PCB, BCC+ & BCC++ allow greater thermal enhancement compared with other thin and small outline packages (e.g. TSSOP). In addition, the ground ring in BCC++ provides lower ground inductance (for more product data, please refer to Leadless Package). |
| |
| LGA |
| LGA (Land Grid Array), an offshoot of BGA without solder balls, is another leadless package. LGA has the advantage of flexible routing to implement both electrical and thermal enhance-ment (for more product data, please refer to Leadless Package). |
| |
| Low & Thin BGAs |
| Low & Thin BGAs (L(F)BGA, T(F)BGA, and V(F)BGA) are the fine ball pitch (as small as 0.5mm) and thin profile (thinner than 1mm) types of BGA as defined by JEDEC. These packages are capable of customized design, and therefore can be fabricated to near chip size. L(F)BGA is applicable to 3D MCM (also known as Stacked CSP). It can stack the chips nearly twice the size as the package. SCSP is suitable for the integration of hybrid memory ICs (for more product data, please refer to BGA, MCM, & SCSP). |
|
| Key Features |
| |
|
| |
| 1. Packaging efficiency=(total chip area)/(package area). |
| 2. 3D MCM (Stacked dice). |
|
