Flip Chip  FC-CSP




Product Overview
 
FC-CSP (Flip Chip Chip Scale Package) offers chip scale capacity for the I/Os of 200 and less. FC-CSP provides better protection for chip and better solder joint reliability compared with direct chip attach (DCA) or chip on board (COB). FC-CSP is more superior to known good die (KGD) in low-cost test and burn-in, and performs comparable electrical function with KGD. FC-CSP features thin and small profile, and lightweight packages.

Applications include RFICs and memory ICs. ASE provides packaging service for any customer-designed size at the ball pitches ranging from 0.5 to 1.0mm, and the I/O from 16 to 200. The types of encapsulation of FC-CSP are underfill type and overmold.



Application
 
Consumer:
Camcorder, Digital Camera, DVD, etc.
 
Computer:
Voltage regulators, High-Speed Memory, Card PC, Peripherals, etc.
 
Telecommunications:
Pagers, Cellular handsets, etc.



Features
 
  • Thinner Profile
    "Wafer Thinning" capability (down to 8 mils) to support packages thinner than 1.0 mm package.
  • Substrate
    2-layer BT laminate substrate is used to reduce overall package cost.
  • Improved Performance
    Thin core (100 um) substrate & via-on-pad design can be adopted to achieve better electrical performance.
  • Robust Structure
    Overmolded process can enhance throughput, component and board level reliability.



Reliability
 
Package Level
MSL level 3 220°C
TCT-B 1000 cycles
THT 1000 hrs
HTST 1000 hrs
PCT 168 hrs
HAST 100 hrs
 
Board Level
 
 
Weibull distribution of FC-CSP 48L with different surface finish and 0.30 mm dia. Sn 63/Pb 37 solder ball. Test Condition: -40°C~125°C air-to-air.



Design Rule
 
Packaging Capability/Outline Dimension (All units are in mm.)
 
The alphabetical notation means:
A Pkg Overall thickness
A1 Stand-off
b Ball diameter
c Substrate thickness
e Ball pitch
 
FC-CSP
Pkg size Lead count A A1 b c e
D1 E1
7 7 48/49 1~1.4* 0.2 0.3 - 0.75/0.8
8 8 64 1~1.4* 0.2 0.3 - 0.8
11 11 100 1~1.4* 0.4 0.45 - 1
15 15 196 1~1.4* 0.4 0.45 - 1
 
(1mm=39.37mil; 1mil=25.4um)
*Depended on the die and substrate thickness



Performance
 
Electrical (Contact ASE R&D for details.)
 
Thermal
 
The thermal data of flip chip packages is related to several factors; number of substrate layers, substrate thickness, substrate material, die size, and I/O pad layout. (Contact ASE R&D for details.)



Standard Process/Materials
 
FC-CSP/FC-BGA/FC-CBGA
Wafer bumping  
Wafer mount  
Wafer saw/clean  
Flip chip & reflow  
(Flux clean)  
Underfill  
Underfill curing  
Top side laser marking  
Solder ball mount Solder ball: Sn/Pb=63/37
Reflow  
Flux clean Flux: Water soluble
Singulation (for FC-CSP only)
Final visual inspection (Gate)  
Packing Bakable JEDEC tray
 
Optional process: Dry packing/molding/heat spreader planting (for FC-BGA)



Package Offering
 
Pkg type Pkg size Ball pitch Lead count
FC LFBGA 6x8 0.8mm 48
FC LFBGA 6x8 0.75mm 48
FC LFBGA 7x7 0.8mm 48
FC LFBGA 7x7 0.75mm 49
FC LFBGA 8x8 0.8mm 144
FC LFBGA 11x11 1.0mm 100
FC LFBGA 15x15 0.8mm 120
* MFC LFBGA 4x4 0.8mm 16
* MFC LFBGA 7x7 0.8mm 49
* MFC LFBGA 8x8 0.8mm 49
* MFC LFBGA 7x7 0.5mm 100
* MFC LFBGA 7x7 0.5mm 113
* MFC LFBGA 11x11 1.0mm 100
* MFC LFBGA 14x22 0.8mm 209
 
*MFC BGA: Molded only Flip Chip BGA



Packing & Shipping
 
Tube or tray or other materials
 
FC-CSP (JEDEC Tray)
Pkg size (mm) Row Column Total QTY Temp(°C) Vendor
7x7 13 32 416 150 PEAK
8x8 12 30 360 140 Daewon
11x11 8 12 96 150 PEAK
15x15 7 18 126 165 Daewon



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