| Product Overview |
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| The need for high density, high performance, and cost effectiveness has sped up the deve-lopment of System on a Chip (SoC) and System in a Package (SiP). The most current assembly technology is the Multi-chip module (MCM) package. It integrates different func-tions of chips such as microprocessors, memory, logic, optic ICs and capacitors, onto mini-substrates, instead of placing individual packages onto a large PCB (also known as second level package). |
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| Application |
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ASE's MPBGA (Multi Package Ball Grid Array) utilizes the MCM assembly method. It employs the latest IC packaging technology for high-density products. The electrical and thermal performance and the affordability of the MPBGA package enable system designers to integrate several devices (Known Good Die) onto a single IC package. ASE has begun volume production since Q1 of 2002.
The integration of several semiconductor technologies onto a single MPBGA package offers excellent advantages for many applications where size, weight, electrical performance and board density are critical requirements. The high-speed performance and improved thermal capability of the MPBGA package are also excellent for personal computering, networking, graphic chips, data communication, consumer IC and telecommunication, analog/digital, ASIC and memory applications. |
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| Features |
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 Known good die
Reduced size and weight
Improved Silicon efficiency
Reduced signal delay & noise
Lower power consumption
Enhanced speed & bandwidth
Excellent electrical performance by shrinking the board level interconnection into a package level
Customized-design of substrate routing
Space savingSystem integration |
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| Reliability |
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| Package Level |
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| MPBGA (31x31 PBGA+12x12 CSP) |
| MSL |
JEDEC level 3 30°C/60%, 192 hours, IRx3, 220C |
| PCT |
121°C/100%/2 atm, 168 hours |
| TCT |
-65°C~150°C, 1000 cycles |
| HAST |
150°C 1000 hours |
| HTST |
85°C/85% 100 hours |
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| Lead Free Capability (Q3/2002 ready) |
| MSL |
JEDEC level 3 30°C/60%, 192 hours, IRx3, 260C |
| PCT |
121°C/100%/2 atm, 168 hours |
| TCT |
-55°C~125°C, 1000 cycles |
| HAST |
150°C 1000 hours |
| HTST |
85°C/85% 100 hours |
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| Board Level |
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| MPBGA (35x35 PBGA+12x12 CSP) |
| Temp cycle |
-40°C~125°C |
No failure 702 cycles (W/O under fill) |
| Temp cycle |
-40°C~125°C |
No failure 1300 cycles (W/O under fill) |
| Bending |
1mm deflection/1Hz |
63.2% failed 272200 cycles (W/O under fill) |
| Drop |
1m Height |
100 drops no failed between CSP |
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| SPBGA (45x45 SPBGA) |
| Temp cycle |
-40°C~125°C |
No failure on 1st layer until 868 cycles |
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No failure on 2nd layer until 950 cycles |
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No failed on 3rd layer until 2044 cycles |
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| Design Rule |
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| Item |
Criterion |
| Mold edge to package edge |
1 mm min. |
| Mold edge to CSP edge |
0.3 mm min. |
| CSP edge to package edge |
0.1 mm min. |
| Passive component to package edge |
1 mm min. |
| Fiducial mark for SMT |
0.5 mm min. |
| No. of fiducial mark |
2N-1 (N: No. of CSP) |
| Position of fiducial |
Mid-point of two point should be package center |
| Solder ball edge to package edge |
0.6 mm min. (CSP package) |
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| Performance |
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| Electrical Characterization (Contact ASE R&D for details.) |
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| Thermal |
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| Stack Package BGA (SPBGA) |
| Pkg size |
45x45 mm |
| Pitch |
1.0 mm |
| DIE#1 |
300x300 mil |
| DIE#2 |
300x300 mil |
| DIE#3 |
400x400 mil |
| Substrate (layers) |
4L/2L/4L |
| Substrate thickness |
0.56/0.56/0.56 mm |
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| PCB Conditions (JEDEC JESD51-7) |
| PCB layers |
4L |
| PCB dimensions |
101.6x114.3 mm |
| PCB thickness |
1.6 mm |
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| Simulation Conditions |
| Power dissipation |
10W/DIE#1,5W/DIE#2,5W/DIE#3 |
| Ambient temperature |
70°C |
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| Multi Package BGA (MPBGA) |
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| Package Conditions |
| Pkg type |
BGA484L/LBGA 124L |
| Pkg (BGA) size |
35x35 & 31x31 mm |
| Pkg (LBGA) size |
12x12 mm |
| Pitch |
BGA 1.0 mm/LBGA 0.8 mm |
| D6 |
300x300 mil |
| D6 |
346.5x346.5 mil |
| DDR (x2) |
361.4x206.7 mil |
| Substrate (layers) |
4L |
| Substrate thickness |
0.36 mm |
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| PCB Conditions (JEDEC JESD51-7) |
| PCB layers |
4L |
| PCB dimensions |
101.6x114.3 mm |
| PCB thickness |
1.6 mm |
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| Simulation Conditions |
| Power dissipation |
3W/D6,1.5W/DDR |
| Ambient temperature |
55°C |
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| Standard Process/Materials |
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| Wafer back grinding (Option) |
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| Wafer mount |
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| Wafer saw/clean |
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| 2nd optical (Gate) |
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| Die attach |
A1 Epoxy: ABLESTIK 2100A; Substrate: BT resin |
| Epoxy cure |
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| Wire bond |
Gold wire: 99.99% Au |
| 3rd optical (Gate) |
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| Mold |
M1 Compound: SUMITOMO-7720TA |
| Post mold cure |
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| Top side laser marking |
TECA white 460 |
| Ball mount |
63 Sn/37 Pb |
| Reflow |
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| Flux cleaning |
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| Singulation |
Sn/Pb or Sn/Cu |
| Testing |
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| Solder paste print |
No clean solder paste |
| Surface mount |
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| Reflow |
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| Under fill (Option) |
U1 |
| Under fill cure (Option) |
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| Testing |
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| Final visual inspection (Gate) |
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| Packing |
Tray or tube |
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| Package Offering |
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| MPBGA (Multi Package BGA) |
| Pkg size |
Lead count |
A |
A1 |
b |
c |
e |
| D1 |
E1 |
| 31 |
31 |
484/696 |
2.26 |
0.4 |
0.5 |
0.56 |
1.0 |
| 31 |
31 |
433 |
2.51 |
0.6 |
0.75 |
0.56 |
1.27 |
| 35 |
35 |
484 |
2.51 |
0.6 |
0.75 |
0.56 |
1.27 |
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| MPBGA (Multi Package BGA) |
| Pkg size |
Lead count |
A |
A1 |
b |
c |
e |
| D1 |
E1 |
| 15 |
15 |
340 |
2.0 |
0.23 |
0.3 |
0.21 |
0.65 |
| 45 |
45 |
972 |
4.6 |
0.5 |
0.6 |
0.56 |
1.0 |
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